Quantum Weekly: June 19–26, 2026

The quantum week from June 19 at 10:33 a.m. to June 26 at 10:00 a.m. (UTC-05:00) was dominated by a policy shock: the White House put a 2028 fault-tolerant quantum computer target, federal post-quantum cryptography deadlines, and DOE logical-qubit specifications into the same operating frame. The technical research signal matched that frame unusually well. The most useful papers this week were not broad "quantum advantage" claims; they attacked the plumbing of fault tolerance: qLDPC layout, decoding, mid-circuit measurement, calibration, and logical-processor architecture.

President Donald Trump signed two quantum-related executive orders in the Oval Office on June 22: EO 14413, "Ushering in the Next Frontier of Quantum Innovation," and EO 14412, "Securing the Nation Against Advanced Cryptographic Attacks."12 The first order establishes QC-ADDS, a national mission to deliver at least one fault-tolerant quantum computer for scientific research to a Department of Energy national laboratory, with a 2028 target.1 Reuters reported Michael Kratsios, director of the White House Office of Science and Technology Policy, saying, "We believe this can happen by 2028."3

EO 14412 turns post-quantum cryptography from a background cyber-risk item into a federal migration calendar. Federal agencies must migrate High Value Assets and high-impact systems to NIST-approved post-quantum key-establishment standards by December 31, 2030, and to post-quantum digital-signature standards by December 31, 2031.2 NIST must complete a PQC pilot migration project by December 31, 2027, and the Federal Acquisition Regulatory Council must propose rules requiring federal contractors to comply with NIST FIPS post-quantum standards by December 31, 2030.2 For investors, that matters because procurement timing is now easier to model than scientific timing.

The DOE follow-through came two days later. Quantum Computing Report said the Department of Energy launched "Quantum Genesis" on June 24 with a milestone-driven hardware competition targeting 150-250 logical qubits, logical error rate of 10^-8, and 2028 delivery.4 Those numbers are more useful than the phrase "fault tolerant" by itself. They imply a benchmark regime: not just more physical qubits, but logical qubits with an error budget tight enough to run serious scientific workloads.

The orders also sit on top of the May 2026 CHIPS Act quantum portfolio. The Department of Commerce signed letters of intent with nine quantum companies for $2.013 billion in proposed federal incentives, including $1 billion for IBM to establish a quantum foundry subsidiary, $375 million for GlobalFoundries to build a domestic quantum foundry, and roughly $100 million each for Atom Computing, D-Wave, Infleqtion, PsiQuantum, Quantinuum, and Rigetti, plus $38 million for Diraq.5 The U.S. government would receive minority, non-controlling equity stakes in the awardees.5

That equity model is the political fault line. Michael Spencer of The Quantum Foundry criticized the structure as government "picking winners" and argued that equity stakes create conflicts of interest in frontier science funding.6 WisdomTree's Christopher Gannatti made the cleaner investor point: "No executive order repeals the laws of physics," but orders can reduce friction, create procurement pipelines, and signal the government as a long-term buyer.7 That is the right split: the orders do not make FTQC easier; they make demand more legible.

The market reaction treated legibility as a catalyst. Fortune reported that Quantinuum rose roughly 13-15% on the first trading day after the signing, Infleqtion rose about 12%, IBM gained about 5%, and D-Wave rose about 2%, while the Nasdaq fell 2.2% and the S&P 500 dropped more than 1.4%.8 Seeking Alpha separately reported that Quantinuum and Infleqtion led the quantum rally after the orders.9 The caution is simple: policy can pull timelines forward in budgets and procurement documents before hardware curves have moved.

IQM Quantum Computers had the most concentrated company week. Real Asset Acquisition Corp. shareholders approved the IQM business combination on June 25, with 13,687,335 votes in favor, 800,760 against, and 306 abstentions on the business-combination proposal; the meeting had 14,488,401 shares present out of 23,000,000 shares entitled to vote.10 After closing, IQM is expected to list American depositary shares on Nasdaq Global Market under ticker IQMX.11 The deal implies an approximately $1.9 billion valuation and includes a $146 million PIPE commitment; the maximum pro forma cash figure before redemptions is $477 million.11 The missing number is redemption rate. Without it, the headline vote does not yet tell investors how much cash IQM actually brings onto the balance sheet.

IQM also announced a quantum-error-correction result tied to arXiv:2606.19482, "Nearest-neighbour gates are all you need: High-rate quantum low-density parity-check codes on a planar grid."12 The paper was submitted on June 17, before this issue's coverage window, so it is not a current-window paper pick. The company announcement is current-window news. IQM said the directional tile codes use nearest-neighbor iSWAP gates already native to its Crystal processor and report up to a 1,000x reduction in logical error rate versus rotated surface-code memories at roughly 30 circuit qubits per logical qubit.13 The useful read is not "surface code is dead." The useful read is that superconducting qLDPC work is being forced into manufacturable planar constraints rather than abstract connectivity assumptions.

QuEra Computing made the other roadmap move. QuEra announced a Gigaquop-class fault-tolerant roadmap on June 25, targeting 2028-2029 for a system with more than 1,000 logical qubits, logical error rate of 10^-9, and more than 20,000 physical qubits in a single processing core.14 QuEra also launched an FTQC Founders Circle for enterprises, HPC centers, and government organizations to co-design applications.14 Andy Ory, QuEra's CEO, said Libra brings fault tolerance to the cloud in 2028 and the next generation will scale it by orders of magnitude.14 That is now a direct comparison point against DOE's Quantum Genesis target: QuEra is talking 1,000+ logical qubits and 10^-9 logical error rate; DOE is talking 150-250 logical qubits and 10^-8 by 2028.

Quantinuum announced a strategic collaboration with HPE on June 21 to integrate quantum computing with HPC and AI infrastructure, including hybrid reference architectures, application workflow validation, and enterprise customer engagement.15 Quantinuum will provide quantum-system access, technical expertise, and developer environments, while HPE will provide HPC systems and deployment capability.15 For researchers, that collaboration is less about a new device metric than about the control plane around future QPUs: scheduling, workflow integration, and hybrid execution.

Alice & Bob and Bull, an Atos advanced-computing and AI business, signed a memorandum of understanding on June 24 covering research, product innovation, software development, and commercial development for quantum-HPC integration.16 Bull's Qaptiva platform will support cat-qubit simulation and execution as part of the collaboration.16 Alice & Bob also said on June 26 that it had been selected for the French Tech Next40 for a second consecutive year, with more than 250 employees, more than 70 patent families, and cumulative financing of EUR180 million.17

Quantum Computing Inc. closed its acquisition of NHanced Semiconductors on June 23 for $73.1 million in cash and stock, plus up to $72 million in earnout consideration.18 QUBT said the acquisition starts its Fab 2 manufacturing facility and accelerates commercialization of its thin-film lithium niobate photonic integrated-circuit platform.18 This belongs in the same infrastructure bucket as the U.S. foundry awards: quantum vendors are trying to control fabrication and packaging bottlenecks before useful logical machines arrive.

The current-window paper set is unusually coherent. If the policy section defined the demand signal, the papers defined the engineering agenda: reduce overhead, make control loops fast enough, and fit high-rate codes into real hardware.

Bunny Codes attack superconducting QEC through the native gate set rather than long-range couplers. Runshi Zhou and coauthors submitted arXiv:2606.22853 on June 22, presenting a qLDPC code family implementable on two-dimensional nearest-neighbor superconducting connectivity with CNOT plus CXSWAP gates.19 The best Bunny Codes with weight-6 stabilizers under periodic boundary conditions reach about 3x the code rate of the toric code, and open-boundary versions reach about 2x the rate of the rotated surface code.19 Circuit-level simulations report logical error rates an order of magnitude lower than toric codes at comparable code rates.19 Evidence strength: simulation and code construction, not device demonstration.

Routing Codes go after the wiring geometry. Jiaxuan Zhang, Zhao-Yun Chen, Peng Duan, Jia-Ning Li, Tian-Hao Wei, Qing-Yang Hou, Wei-Cheng Kong, Yu-Chun Wu, and Guo-Ping Guo of the University of Science and Technology of China submitted arXiv:2606.25330 on June 24.20 The paper proposes qLDPC codes with rates comparable to bivariate bicycle codes while reducing qubit connectivity, shortening non-local coupling lengths, and making all non-local couplings mutually parallel.20 Under circuit-level simulation, weight-7 Routing Codes reduce physical-qubit overhead by about 8x relative to surface codes at the same logical error rate.20 Evidence strength: simulated hardware-centric layout; strong relevance for superconducting multilayer wiring, but still pre-experimental.

Rapid cavity-based mid-circuit measurement in neutral atoms is the experimental paper to read first. Tsai-Chen Lee, Jacquelyn Ho, Yue-Hui Lu, Tai Xiang, Nathaniel B. Vilas, Zhenjie Yan, and Dan M. Stamper-Kurn of UC Berkeley submitted arXiv:2606.24869 on June 23.21 The team demonstrated mid-circuit measurements of four qubits with sub-percent infidelity while reducing coherence of a fifth unmeasured data qubit by less than 2%.21 The measurement-and-feedforward cycle time was below 100 microseconds, more than 10x faster than typical neutral-atom systems near 1 millisecond.21 Evidence strength: real experiment with small qubit count, directly relevant to QEC control loops.

Hierarchical Logical Processor with shuttle buses proposes a compromise between surface-code locality and qLDPC efficiency. Zi-Han Chen, Ming-Cheng Chen, Chao-Yang Lu, and Jian-Wei Pan of USTC submitted arXiv:2606.22594 on June 21.22 The architecture concatenates a high-rate quantum CSS code with the rotated surface code, requiring long-range connectivity only once every Θ(d0) rounds of level-0 error correction.22 At physical error rate p=10^-3, an HLP based on a [[256,194,4]] code achieves 3-4x higher qubit efficiency than standard rotated surface code, and it reduces space overhead by 100-200 physical qubits per logical qubit versus yoked surface code on the same level-1 code.22 Evidence strength: architecture proposal and analysis, not hardware.

Vibe Calibration brings language agents into hardware bring-up rather than algorithm design. Huikai Xu and coauthors submitted arXiv:2606.22376 on June 21, reporting autonomous calibration of 108 out of 112 qubits on a superconducting processor in 4.7 hours.23 The paper claims a 4-5x speedup over manual calibration and reports agreement with expert manual calibration on 14 of 16 qubits in a cross-validated subset.23 Evidence strength: system demonstration on a large superconducting processor; portability still depends on low-level hardware-interface adaptation.

STAR architecture from QuEra and Harvard connects this week's roadmap announcement to an application-level FTQC design. Refaat Ismail, Milan Kornjača, Hong-Ye Hu, Nishad Maskara, Sheng-Tao Wang, Hengyun Zhou, and Chen Zhao submitted arXiv:2606.25011 on June 23.24 The paper uses bicycle chain codes and STAR injection for neutral-atom hardware, estimating that an 8x8 transverse-field Ising simulation to T*≈8 requires 2,240 physical qubits and about 200 seconds per shot.24 The authors report about a 5.5x space reduction versus surface-code STAR at comparable speed.24 Evidence strength: end-to-end architecture estimate aligned with QuEra's platform, not a device run.

Three smaller but useful papers round out the week. Korea University researchers submitted a compact surface-code architecture for eight-to-three CCZ magic-state distillation that preserves single-fault detection while reducing spatial cost relative to the Gidney-Fowler design.25 Kenny Heitritter, James Brown, and Tarini Hardikar used LLM-driven evolutionary program synthesis to find distance-5 generalized superfast fermion-to-qubit encodings, reporting 4.2-5.0x fewer data qubits than a per-mode Jordan-Wigner plus [[25,1,5]] surface-code route at p=10^-3 under code-capacity assumptions.26 Zidu Liu and Florian Marquardt introduced Structured Concept Evolution, pairing an LLM with algebraic mutation grammar to discover lifted-product CSS qLDPC code families under code-capacity depolarizing noise with BP+OSD decoding.27

The pattern is clear enough to act on: qLDPC is the dominant theory thread, but the strongest papers are the ones that remove a specific hardware obstacle. Bunny Codes and Routing Codes address connectivity and layout. UC Berkeley addresses selective measurement and fast feedforward. Vibe Calibration addresses bring-up labor. STAR addresses the algorithm-to-architecture bridge. This is the stack that has to harden if 2028 procurement targets are going to survive contact with machines.

For IQM, the next material disclosures are redemption rate, closing date, and first trading date for IQMX. The shareholder vote was decisive, but cash after redemption will determine how much runway the listing actually provides.10

For U.S. policy, the next useful document is not another speech. The important follow-up is the detailed technical specification and benchmarking process for QC-ADDS / Quantum Genesis, because those documents will decide which modalities can credibly bid for the first national-lab FTQC systems.4

For company tracking, the actionable gap is simpler: the public FTQC agenda this week was set mainly by IBM-adjacent federal policy, Quantinuum-HPE integration, IQM's listing path, QuEra's roadmap, and qLDPC-heavy research rather than by a single new hardware-record announcement.