Quantum weekly, November 6–13, 2026 | One working processor in three, and two refrigerators joined by 10 km of fiber

Three numbers published this week describe parts of a quantum computer rather than a machine.

IBM put a junction count on its 2029 fault-tolerant system: about 2,000 Josephson junctions per processor, down from roughly 5,000 1. A group led from Tsinghua delivered a universal gate set to a qubit in a second dilution refrigerator through 10 km of optical fiber 2. And a nine-device benchmark found that the largest entangled state passing its test on IBM's 120-qubit Phoenix held 27 qubits 3.

Each of those numbers is a count of parts, multiplied by the rate at which a part fails. Read together, they locate this week's constraint in how many parts have to work at once.

IBM Quantum Starling is due in 2029, with 200 qubits running 100 million hard operations 1. The post restates that target and adds the first published arithmetic for what it takes to build one.

The summary calls the target hard operations; the body of the same post calls it quantum operations.

The load-bearing figure is the junction count. IBM says two changes cut the Josephson junctions per processor from about 5,000 to about 2,000. One is a code improvement: the qLDPC code now needs five connections per qubit instead of six. IBM reports 20 to 100 times lower logical errors with the change.

The other is coupler design. Junctions matter to manufacturing because yield compounds over them.

At a junction yield of 99.95%, IBM calculates that about 1 processor in 12 will come out fully functional with 5,000 junctions. At 2,000 junctions, about 1 in 3 will.

That is the arithmetic of independent failures. A single junction survives with probability 0.9995, so 2,000 of them survive together at 0.9995^2000. That product is 0.368, or one in 2.7. For 5,000 junctions it is 0.082, or one in 12.2. IBM's figures land on the same curve.

The consequence is that a 60% cut in junction count multiplies the number of working processors by four. The count sits in the exponent, so it dominates the per-junction yield it is multiplied by.

The code change carries a second number. IBM puts the modular qLDPC architecture at about 10 times fewer physical qubits than earlier approaches for the same logical error rate. Fewer qubits per logical qubit means fewer junctions per logical qubit, and the yield arithmetic applies again at the next level up.

The coupling hardware moved too. The chip-level c-couplers that link distant qubits now show quality factors above 10 million, past the Starling requirement. The stack has gone from two coupler layers to three, with four planned. The couplers are 20 mm long, which loosens the density requirement on the qubit grid.

The result is a processor that can be built at a yield worth quoting.

The same post gives the gap to its own targets, in its own numbers.

IBM Quantum Loon, the test chip for the qLDPC components, has qubit relaxation times of about 200 microseconds. Its reset time constants are 20 to 40 nanoseconds, and its median gate error is near 0.3%. Starling's targets are a T1 in the millisecond range and gate errors in the low 0.01% range 1.

Loon is therefore roughly five times short on coherence and about 30 times short on gate error. IBM writes that it routinely measures errors in the high 0.01% range on Heron and Nighthawk, reaching 0.04%. It also says separate test devices hold coherence times in the single-digit millisecond range. The claim is that the physics transfers. The post leaves the transfer as the next step.

Interconnect is the other open requirement. Starling needs more than 100 l-couplers per module at 0.1% error, across as many as 12 cryogenic modules. Two Nighthawk r2 processors are now cooling with l-couplers attached, at quality factors of 1 to 2 million 1.

IBM states the link error for that pair as about 1% on average, with a best of 0.7%. That is the measurement to set against the 0.1% requirement, ten times further down.

The wiring carries its own scale. Each cryostat bay is designed to hold up to 0.96 miles of trace. A Nighthawk r3 will need about 3.84 miles. Cryogenic control ASICs now match room-temperature electronics on gate performance, after an earlier version controlled about half of a Heron processor's two-qubit gates.

The decoder has closed. IBM says its Relay-BP decoder now meets Starling's requirements for memory and measurement, and that a 2-nanometer decoder ASIC is in development.

IBM writes that the main architecture for Starling has not changed and that the pathway has been validated. Meeting an architecture and meeting a specification are separate claims, and the post publishes the evidence for both side by side.

IBM's other dated item was a deployment. On 6 November it unveiled a Quantum System Two in Chicago, at Hyde Park Labs, hosted by the University of Chicago 4.

The system runs IBM Quantum Nighthawk. IBM calls it the company's most advanced system available, which describes the shipping product line. The same chip family appears in this week's benchmark paper.

What changed is where the machine sits. It is IBM's first quantum computer in Illinois and the anchor system of the National Quantum Algorithm Center. It will move to the Illinois Quantum and Microelectronics Park when construction finishes, and IBM restated a 750-job FutureNow center at the park.

The release carries no new qubit count, fidelity or error rate. Its news is access: Illinois researchers get a machine in their own state, running hardware that is also sold by the hour elsewhere.

The week's most concrete hardware result moves the control layer out of the refrigerator.

A group at Tsinghua's Institute for Interdisciplinary Information Sciences sent microwave control signals between two dilution refrigerators as light, over 10 km of fiber. Its collaborators were at USTC, ShanghaiTech, the Beijing Academy of Quantum Information Sciences and the Hefei National Laboratory 2.

The conversion happens twice. In the first refrigerator, a microwave-to-optical transducer turns the control waveform into an optical sideband. A second sideband, generated from the same laser, travels beside it as a phase reference. In the second refrigerator both beams fall on a photodiode, and the beat between signal and reference regenerates the drive at the right frequency and phase.

The receiver needs no synthesizer or local oscillator. It also needs no attenuator chain, because fiber enters a cryostat with less heat load than coax. The measured isolation between output and input ports was −39.4 dB.

The group delivered a universal gate set this way to a transmon qubit and a cavity qubit in the second refrigerator, then entangled the two. Average fidelity per elementary gate was 95.36 ± 0.13%. The Bell state they prepared had a fidelity of 80.6% 2.

One condition belongs beside the number. The fiber is 10 km long, and the figure shows it wound on a spool. The experiment proves that 10 km of fiber preserves the phase relationship. Two laboratories 10 km apart were not operated as one machine.

Earlier work had carried coherent microwave pulses between resonators in two refrigerators over 1 km of fiber, with two electro-optic transducers matched to each other. No qubit was driven through that link. This link is ten times longer, and it derives both the signal and its reference from one laser, so laser phase noise and fiber fluctuations cancel between them.

The distinction matters because the requirement it addresses is modularity inside a single system. Superconducting processors are running out of cryostat: every qubit needs its own control and readout lines, and the wiring, heat load and volume cap what one refrigerator holds. IBM's answer is 12 modules in linked cryostats. The optical link is a different answer to the same problem, and the first demonstrated with a full gate set at this distance.

A group from Basque research institutions and universities ran one benchmark across nine commercially accessible processors from five vendors. Every run went through cloud access, with each provider's default compilation and no error mitigation 3.

The test prepares a Greenberger–Horne–Zeilinger state and estimates its fidelity. It then searches for the largest size at which that fidelity stays compatible with the genuine multipartite entanglement threshold of one half. That size is N*.

The results separate register size from usable size. IBM's 120-qubit Phoenix reached N* = 27, or 23% of its register. Its 156-qubit Basque Country and Pittsburgh machines reached 24 and 21. IQM's 54-qubit Emerald reached 20, and its 20-qubit Garnet reached 13.

The trapped-ion outlier was AQT's 12-qubit Ibex, which passed at its full register with a fidelity of about 0.71. Rigetti's Cepheus reached 4 of 107 available qubits, and OQC's Qmio 3 of 32.

The decision rule moves the result as much as the hardware does. Requiring the entanglement to be certified, rather than merely compatible with the threshold, cut the devices that succeed at any tested size from nine to four. IBM's Pittsburgh passes the benchmark up to 21 qubits and certifies entanglement at none of the sizes tested.

Calibration data predict little either way. Per-qubit GHZ error runs from 2.8% to 20%. Its ratio to the median calibrated two-qubit error spreads across a wide band around the diagonal.

The ranking inside a single vendor shows the same thing. IBM's four processors span 18 to 27 passing qubits while their median two-qubit error varies from 0.157% to 0.319%. Rigetti's Cepheus reports a median two-qubit error of 1.312% and passes at 4 qubits. AQT's Ibex reports 1.570% and passes at 12, because its all-to-all connectivity removes the swaps a GHZ circuit needs on a heavy-hex lattice.

Three conditions limit what this establishes. The benchmark measures state preparation under default compilation, which is what a cloud user receives and less than a tuned device can do. The experiments ran between July and September 2026, so the numbers describe those configurations. And GHZ fidelity is one axis: nothing here measures whether a processor can run a circuit anyone wants.

Google's dated output this window is a preprint.

Google DeepMind and Google Quantum AI built a library of quantum programs in the Lean theorem prover. They then set Gemini 4 agents to synthesize new programs against formal specifications 5. The Lean kernel checks each candidate for correctness, and a separate comparator checks its cost. A program that passes has both properties proved.

The reported gains are against prior baselines: 290-fold on quantum arithmetic, 2.55-fold on parallel search, and 11-, 8- and 2.5-fold on simulations for fusion, photochemistry and drug metabolism.

The mechanism is the part worth carrying away. A quantum algorithm's cost can be checked classically even when its output cannot, because cost is a property of the circuit rather than of the physics it simulates. That lets a search loop run at scale with a proof at the end of every attempt.

Two limits belong with the claim. The work is a preprint submitted on 6 November and revised on 9 November. Its improvements are measured against the baselines the authors chose.

Google's own blog still lists its 15 October magic-state cultivation post as the newest 6. The company's hardware program published nothing new this week.

The same week produced two results that lower the cost of simulating a quantum computer classically. Both bear on how much of an advantage survives.

Yunchao Liu, at IBM Research in Cambridge, Massachusetts, worked with co-authors at EPFL, the National University of Singapore, Caltech and Virginia Tech. They gave a polynomial-time classical algorithm for estimating out-of-time-ordered correlators in one-dimensional random circuits 7.

OTOC estimation had been proposed as a candidate for verifiable quantum advantage, and earlier work found it hard for tensor networks and Monte Carlo. The new algorithm organizes the correlator into a series whose leading term covers permutation histories, and argues that chaos suppresses the rest. On 1D circuits it estimates the four-point and eight-point correlators with a higher signal-to-noise ratio than Google's recent two-dimensional experiments at larger depths. The authors leave 2D open.

Craig Gidney and Cody Jones gave a classical simulator for CSS circuits, built from X, Z, measurement and CNOT gates, at constant cost per gate 8. The simulator is a local hidden variable model. The authors use a Bell inequality to show it cannot be extended to Hadamard, CZ or S gates.

Set beside Google's 290-fold arithmetic reduction, the week's algorithmic news runs in both directions at once. Cheaper circuits lower what the hardware must do; cheaper classical algorithms lower what counts as beyond it. The balance is struck problem by problem, and this week moved both sides.

Quantinuum's dated item was an integration milestone.

Reimei, the machine installed at RIKEN, has finished its upgrade from System Model H1 to H2 9. It runs inside the JHPC-quantum project funded by NEDO, as the quantum element of a hybrid platform that also includes RIKEN's Fugaku supercomputer and its ROQUO GPU system.

The release describes two research projects that began before public service launch. One trains an AI model on Reimei-generated data for magnetism simulation. The other combines Reimei, Fugaku and an NVIDIA agent on ROQUO for biomolecular simulation. Neither has published results, and the release gives no fidelity or qubit figures for the upgraded machine.

The commercial part is a memorandum of understanding. Quantinuum and RIKEN will work with Japanese universities and domestic suppliers on a fault-tolerant machine described as "Made with Japan". A separate agreement with SoftBank covers connecting quantum computers to AI data centers in Japan.

The arrangement puts a machine in a national laboratory, attaches a domestic supply chain to it, and adds a services partner to sell the output. The Reimei release names all three at once.

IonQ published three items, none of them technical.

On 9 November it named Carahsoft as its public-sector distributor, so federal agencies can buy IonQ systems through Carahsoft's reseller network 10. On 10 November it reported placement in the "Market Shaper" quadrant of Gartner's first Emerging Market Quadrant for quantum computing. It quoted Gartner's description of such vendors as lower-risk bets for buyers 11.

On 13 November it replaced its finance leadership. Gary Merrill, until now chief financial officer of Commvault, becomes CFO in early December. Thomas Austin, formerly chief accounting officer at Juniper Networks, takes a new CAO role immediately, and Inder Singh steps down from both roles 12.

The stated reason is the transition from a quantum computing company to a full-stack platform and foundry, and the accounting demands of that scale. The chief executive's quote credits Singh and describes the new hires as bringing public-company finance experience for the path to profitability. The release gives no reason for the timing, eight days after the company raised its full-year guidance.

Three more results, each with its number.

Zeki Can Seskir and two co-authors updated their census of quantum technology companies. The dataset now holds 1,092 companies founded with a quantum focus, of which 935 remain active, against 441 in the 2022 version 13. Computing software and applications remain the largest field, and suppliers and supporting businesses account for almost a third of active companies.

A group led by Gilberto Borges reported the entanglement-based segment of Slovakia's national quantum communication infrastructure, connecting four cities over deployed telecom fiber. After the full post-processing chain, keys were delivered in real time at 13.5 bit/s over 109 km, and at 4.3 bit/s across 32.1 dB of accumulated loss between two cities with no direct fiber link 14.

A group at QuTech in Delft, including Ronald Hanson, built an array of 400 silicon T center cavities with an average quality factor of 298, detuned 0.0 ± 1.1 nm from the emitter line. The array raised the median T center signal 6.5-fold, a 42-fold speedup in measurement, and allowed the T center density to be inferred at 4.2 per square micrometer 15.

PsiQuantum published no dated release in this window; its news index carries nothing after 29 October 16.

IBM's next dated item on the Starling path is the decoder ASIC. The larger question is whether Loon reaches a millisecond T1 and a low-0.01% gate error on one device. Those two numbers decide whether the code's five-connection version works at the target logical error rate.

The benchmark's ranking is worth reproducing. A vendor that runs the same GHZ test under its own tuned compilation, and publishes the result, would settle how much of the N* gap comes from default settings.

The 2D OTOC question is open in both directions. A classical algorithm for two-dimensional circuits would remove a candidate advantage. A hardware demonstration at a size the algorithm cannot reach would restore it.

Quantinuum's Reimei service launch, and the first published results from the two research projects, will show whether the H2 upgrade changes what RIKEN can run.

And PsiQuantum's next dated page, since its last was the 29 October optical switch release.